The trend toward higher speeds for data transmission and manipulation with respect to computers, business machines, and like devices is fast rendering long established designs for connectors and printed circuit board assemblies obsolete. A reason for this is that as data transmission has become digital the rise time of the digital pulses has increased, from milliseconds to nanoseconds (nS). This has led to the various parameters, including resistance (R), inductance (L), and capacitance (C) of the various conductive and dielectric components in printed circuit boards and connectors having a greater affect on signal propagation, delay, signal reflections, and cross-talk between circuit paths, as well as a host of new phenomena adversely affecting signal transmission. The problem is aggravated because in certain widely-used multi-bused architectures such as the versatile backplane bus (VBE) approach, the various conductive path geometries, spacings, path lengths, turns and twists of conductive traces cannot be made equal and thus cannot be made to respond to high-speed pulses in the same way. This problem affects any bus architectures where multiple daughter cards are interconnected through a backplane. Additionally, these differences cannot readily be practically compensated for by tradition techniques. Differences in characteristic impedance (Z.sub.0), differences in propagation delay (T.sub.pd) as well as traditional values of R, L, and C all work together to limit transmission speeds within boards and through connectors.
U.S. Pat. No. 3,643,201 granted Feb. 15, 1972 is directed toward the problem mentioned above and utilizes impedance matching and microstrip concepts to interconnect circuit boards through a two-piece connector utilizing signal and ground planes and spacings to maintain an impedance match throughout the circuit. Unfortunately, with respect to many standard bus structures, microstrip techniques and impedance matching frequently can not be employed. In most standard bus systems, a given bus "sees" a wide variety of stubs in the form of connector/daughter board ensembles which are each different in terms of components, loading, lengths and geometries of paths and so forth.
Accordingly, it is an object of the present invention to provide an interconnection concept, including a connector structure and board assembly which facilitates interconnection of circuit paths or digital pulses having high speed characteristics. It is a further object to provide an interconnection assembly capable of handling fast rise time digital pulses with minimum reflection and pulse distortion.
It is still a further object to provide a novel system having bulk conductive and dielectric constituents which minimize, in a quantitative sense, the bulk values of R, L, and C of the interconnection circuit paths and further operate in a qualitative sense to decrease signal delays of signals propagated through the interconnection structure.
It is yet another object to provide a novel connector structure utilizing conventional, low-cost plastic materials in conjunction with readily formed conductive paths to improve connector performance relative to traditional constructions, including the saving of space on boards and the facilitation of placement of transceiver elements or other active devices proximate to, and in one embodiment, within a connector structure to facilitate high speed signal transmission.